A 6.25Gb/s Decision Feedback Equalizer in 0.18¥im CMOS Technology for High-Speed SerDes

In this paper a 6.25Gb/s two-tap half-rate decision feedback equalizer (DFE) is designed and implemented in TSMC 0.18μm CMOS technology. After system-level simulation based on Simulink and pre-simulation, the DFE architecture is designed and corresponding parameters are determined. To achieve high data rate, CML DFFs, summers and multiplex are all designed elaborately. The total area including I/O pads is 0.3×0.5μm
²
. Post simulation results show that the horizontal eye opening of recovered data is 0.7 UI at 6.25Gb/s.