Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC

The design of a CMOS track-and-hold amplifier (THA) for a 6-bit 1-GS/s interpolating flash ADC is presented. Since the goal of the overall project was to determine the performance of a new ADC calibration architecture, the THA was prohibited from being the limiting factor in the performance of the ADC; consequently the THA was required to have at least 56dB of signal-to-noise and distortion ratio (SNDR) at the Nyquist frequency. The THA architecture, design methodology, and supporting simulation results will be presented.