Application specific parallel memory architecture for software defined radio

Ultra-wide multi-lane SIMD technique is being used in accelerating Software Defined Radio (SDR) application, while memory organization and address generation model of classical parallel memory architecture were not optimized for SDR, resulting in low efficiency of SIMD technique. To cope with this issue, this paper proposed an application specific Parallel Memory Architecture for SDR (MPMD-PMA). MPMD-PMA is organized in segment, and the address generation model of segments can be configured to supporting different access patterns for SDR algorithms. To support exploiting varied data level parallelisms in different kernel algorithms, each segment can be partitioned into different domains, each domain contains the same lanes, different domains in the same segment do the same SIMD operations, while the data can be from address-unrelated data blocks. The VLSI implementation of MPMD-PMA and hardware evaluation were proposed. Besides, the performance evaluation has been done in Simulation. The simulation results show the memory access speed up of MPMD-PMA over classical PMA can be dozen.