A FPGA-based low-cost real-time wavelet packet denoising system

Most existing wavelets are irrational, which are inefficient in hardware implementation and have expensive cost of resources. Based on rational wavelets, we establish a real-time wavelet packet denoising system, which greatly improves the implementation efficiency on FPGA chips. The experimental results reveal that rational 9-7 wavelet decomposition hardware area in slices is less than 1/6 of the pipelined 9-7. To get further decrease in resources of the denoising system, we put forward a new threshold algorithm on denoising the coefficients, and it performs nearly the same as Donoho universal threshold algorithm, while consuming much less resources when implementing on FPGA.