FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming

Nowadays, systems are getting harder and harder to develop and maintain. For a long time, researchers have tried to solve these problems by increasing the level of abstraction, but RTL description languages (e.g. Verilog) are still being widely used. This paper proposes Feature Verilog, a novel hardware description language that extends Verilog to support Feature-Oriented Programming (FOP). Feature Verilog does not avoid the detailed description of RTL, but it can organize it in a more reasonable way. We have implemented a prototype pre-compiler for Feature Verilog and used it to re-develop the Open RISC 1200 project. The comparison of our implementation and the original one shows that Feature Verilog can eliminate the duplicate code in the latter implementation effectively.