Sequence pair based voltage island floorplanning

In the nanometer era of VLSI design, high power consumption is considered to be a “show-stopper” for many applications. Voltage Island design has emerged as a popular method for addressing this issue. This technique requires multiple supply voltages on the same chip with blocks assigned to different supply voltages. Implementation challenges force blocks with similar supply voltages to be placed contiguous to one another, thereby creating “islands”. Classical floorplanners assume a single supply voltage in the entire SoC and thus require additional design steps to realize voltage islands. In this paper we present a new floorplanning algorithm based on the sequence pair representation that can floorplan blocks in the form of islands. Given the possible supply voltage choices for each block, the floorplanner simultaneously attempts to reduce power and area of the chip. Our floorplanner integrates the tasks of assigning blocks to different supply voltages and the placing of the blocks in the chip. Compared to previous work, the proposed floorplanner on average reduces the area overhead of the chip by 13.5% with 34% runtime improvement. Additionally we explore the tradeoff between power and area for different floorplan solutions.