VLSI architecture for datapath integration of arithmetic over GF(2/sup m/) on digital signal processors

This paper examines the implementation of finite field arithmetic, i.e. multiplication, division, and exponentiation, for any standard basis GF(2/sup m/) with m/spl les/8 on a DSP datapath. We introduce an opportunity to exploit cells and the interconnection structure of a typical binary multiplier unit for the Finite Field operations by adding just a small overhead of logic. We develop division and exponentiation based on multiplication on the algorithm level and present a simple scheme for implementation of all operations on a processor datapath.