High-level synthesis for multi-cycle transient fault tolerant datapaths

As the advance in semiconductor technology, the tolerance for transient faults caused by particle strike, called SET (single event transient), becomes an important issue, and moreover future technologies bring the possibility of occurrence of long duration errors spanning across multiple cycles of the circuits due to particle strike. In this paper we discuss high-level synthesis for multi-cycle transient fault tolerant datapaths. Clarifying the conditions for multi-cycle error correctability and detectability of multi-cycle transient fault tolerant datapaths, we propose a heuristic algorithm for finding optimal operator binding of k
c
-cycle error correctable / k
d
-cycle error detectable datapaths with minimum operators. The method focuses on only transient faults (not permanent ones), and therefore it can derive appropriate designs necessary and sufficient for tolerance of SET avoiding use of excessive hardware resources.