Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS

Determinant factors of the minimum operating voltage (V
_DDmin
) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. V
_DDmin
consists of a systematic component (V
_DDmin(SYS)
) and a random variation component (V
_DDmin(RAND)
). V
_DDmin(SYS)
is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (V
_DD
). The tuning of the logic threshold voltage of each logic gate is achieved by the sizing of the gate width of nMOS/pMOS. V
_DDmin(RAND)
is minimized by reducing the random threshold variation achieved by increasing the gate width or the forward body biasing. In addition, the temperature dependence of V
_DDmin
is measured for the first time. The temperature for the worst corner analysis for V
_DDmin
should be changed depending on the number of gate counts of logic circuits.