SOI TFET $I_{\rm ON}/I_{\rm OFF}$ Enhancement via Back Biasing

The effect of back biasing on the performance of a planar tunnel field-effect transistor (TFET) implemented on a silicon-on-insulator substrate is investigated. It is found that reverse back biasing reduces the subthreshold swing SS and increases the range of drain current over which SS is less than (
k
_B
T
/
q
)
ln
(10); hence, it is effective for improving the TFET on/off current ratio for low operating voltages (≤ 0.5 V).