Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

In this study, degradation of amorphous silicon thin film transistors (a-Si TFTs) under drain bias (V
_d
) stresses with fixed negative gate bias (V
_g
) has been investigated. For DC V
_d
stress, state creation mechanism dominates the threshold voltage (V
_th
) degradation for relative large negative V
_gd
(V
_g
-V
_d
) while state creation and/or electron trapping dominates for positive V
_gd
. For AC V
_d
stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, frequency and the polarity of V
_gd
. Decreasing stress voltage suppresses state creation and/or hole trapping for -V
_gd
condition, but enhances state creation and/or electron trapping for +V
_gd
condition.