Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits

In this paper, asymmetric drain (ASD) under lap channel do pant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed for low-power high performance (HP) CMOS circuits. The overlap channel at the source and under lap at the drain of this structure reduces the off-state leakage (I
_OFF
), short-channel effects, gate induced drain leakage and improves the on-state drive current (I
_ON
) in comparison to symmetric source/drain (SSD) overlap and under lap structures. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and NOR gates based on these structures show that, although due to under lap at source/drain the reduced I
_OFF
reduces the static power dissipation (P
_stat
) in SSD under lap based logic gates, the reduced I
_ON
due to voltage drop across the under lap lengths increases the propagation delay (τ
_p
) in these gates as compared to SSD overlap based CMOS gates. On the other hand, in the case of proposed ASD under lap the reduced I
_OFF
with improved I
_ON
not only reduces Pstat but also reduces tp in comparison to SSD overlap and under lap based CMOS gates. Thus, the combined advantages of SSD under lap and overlap structures makes the proposed ASD under lap structure suitable for low-power HP CMOS logic circuits. The proposed fabrication flow of this novel device also demonstrates the use of conventional CMOS processes.