CMOS technology for ultra-low power circuit applications

Process and design alternatives for a low power, low voltage CMOS technology are discussed. Reduced chip operating voltage, V/sub dd//spl les/2.5 V, provides low power operation but results in considerably reduced circuit performance. Process options for low power CMOS designs are compared to wafers from an existing 3.3 V, 0.5 /spl mu/m, CMOS technology. Finite element process and electrostatic simulation tools are used to evaluate the following process alternatives; dual work function polysilicon gate electrodes, reduced gate oxide thickness, modified channel doping, and reduced threshold voltage. Process enhancements were based on the modeling parameters, allowing channel lengths to be reduced to the 0.35 /spl mu/m regime, regaining much of the lost performance. Device models are developed using Berkeley simulation tools, to analyze process effects on representative circuits. Test data from wafers run through the optimized low power process is presented.