A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms

This work demonstrates the first fabricated TSV-based die-to-die bonding stacked-layer-number-scalable 3D-SRAM macro. This 3D-SRAM uses a semi-master-slave (SMS) structure and a self-timed differential-TSV signal transfer (STDT) scheme to 1) provide a constant-load logic-SRAM interface across various layer configurations; 2) suppress TSV-induced power and speed overheads; 3) tolerate die-to-die variation, and 4) enable pre-bonding KGD sorting, to improve the speed and yield of universal-memory-capacity platforms. Superior scalability of increasing stacked layer number with small speed overheads is demonstrated in the fabricated 3D-SRAM macro with layer-scalable test-modes. This macro has two SRAM layers that are stacked by a via-last process with die-to-die bonding.