A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (T
_CRIT
). The UDL can be used in any product without any need for customizing. The error to T
_CRIT
is as small as that with replica delay line. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.