A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 psrms jitter

A 5.9-to-8.0 GHz fractional-N digital PLL with TDC histogram calibration, reference doubler compensation and non-periodic DCO dithering is implemented in 55nm CMOS. With reference doubled from 40 MHz, the rms jitter integrated from 1kHz to 10MHz is 0.19ps or 0.4° for a 5825 MHz clock measured at TX output, and the in-band noise floor is -108 dBc/Hz. The reference and worst-case fractional spurs are -94dBc and -70dBc, respectively, and it draws 36mW.