Interfacing VHDL performance models to algorithm partitioning tools

Performance modeling is widely used to efficiently and rapidly assess the ability of multiprocessor architectures to effectively execute a given algorithm. In a typical design environment, VHDL performance models of hardware components are interconnected to form structural models of the large multiprocessor architectures. Algorithm features are described in application specific tools. Other automated tools partition the software among the various processors. Performance models evaluate the system performance. Several iterations may be needed before a suitable configuration is obtained. This paper describes a set of tools that directly interface the VHDL performance models to the algorithm partitioning tools which will significant reduce the time and effort needed to prepare the various models. A methodology that integrates several commercial tools is provided.