Architectural topologies for NoC datapath polymorphic processors

Polymorphic processors attempt to merge the benefits of general purpose processors with performance gains from reconfigurable elements. In this paper, we present a novel polymorphic processor architecture. The integration of a network-on-a-chip (NoC) architecture as a replacement for the processor datapath creates unique requirements for the NoC design. We explore multiple NoC topologies as potential candidates for the creation of a polymorphic processor. A simulator based around the network simulator 2 (ns-2) software platform is created. Standard embedded processor benchmark programs are simulated to explore critical parameters and NoC design decisions impacting the performance of the polymorphic processor.