Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

A robust digitally assisted self-calibration technique is presented to improve the input-referred second-order-intermodulation intercept point (IIP
₂
) of direct-conversion receivers. The low-power, low-noise 1.8-GHz CMOS receiver prototype relies on digital signal processing to improve analog/RF performance with only a minimum hardware overhead and with no performance penalties on the RF front end and analog baseband. The RF front end achieves an IIP
₂
better than 60 dBm without external filters between the LNA and downconversion mixers, has a conversion gain of 38.5 dB, a low DSB noise figure of 2.6 dB, and an IIP
₃
of -17.6 dBm. It consumes 15 mA from a 1.5-V supply, and occupies 1.56 mm
²
on a 0.13-μm CMOS process.