A CMOS 1.0-/spl mu/m two-dimensional analog multirate system for real-time image processing

Two-dimensional (2-D) filters for video signal processing typically operate at high uniform sampling rates and require very large delay-line (DL) memory blocks. By employing 2-D multirate signal processing techniques to reduce the sampling rate, not only the DL memory blocks can be downsized to save silicon area, but also the memory access time can be increased to save power as well. This is demonstrated in this paper considering a 2-D switched-capacitor multirate image processor that realizes (2/spl times/2)nd-order recursive low-pass and high-pass filtering functions employing half of the storage cells that would be needed in a nonmultirate system. Only one type of operational transconductance amplifier with 1-mS transconductance and 120-MHz unity gain bandwidth is needed for both the vertical filter and associated DL memory blocks and the horizontal decimating filter. Fully differential circuit techniques are employed to increase immunity to charge feedthrough injection in the analog storage cells. The complete system has been implemented in a CMOS 1.0-/spl mu/m double-poly technology. The core active area is only 2.5/spl times/3.0 mm/sup 2/, and at 5-V supply and 18-MHz sampling it dissipates 85 mW.