A 2.5 GHz CMOS standard-cell decimation filter for mobile communication

A typical circuit found in modern communication systems is a very high-speed over-sampling analog-to-digital converter (ADC) followed by a digital low-pass decimation filter to transform the received analog information stream into digital domain as early as possible. The low-power digital decimation filter presented here was designed for a ΣΔ ADC structure with 1-bit output at a data rate of 2.56 GHz. The main goal of this investigation is to avoid a transistor-level analog design method (full-custom style) for this fast digital circuit parts and replace it by semi-custom standard cell design. The description starts from system level requirements and goes via VHDL design, synthesis and layout to the back-annotated circuit simulation. Finally, results after layout for different filter structures are given, which demonstrate the correct functionality of the designed decimation filter at the specified operating conditions as well as fulfillment of power consumption goal and design constraints. Extensive simulations and analysis proved that the combination of careful system design, filter topology selection and utilization of latest implementation tools can push the limits of VHDL-based standard-cell design to very high operating speeds at low power consumption without major restrictions on flexibility, time-to-market and reusability.