Operational amplifier design for high-speed pipelined Analog-to-Digital Converters in deep-submicron CMOS processes

In this paper, design challenges of an operational amplifier (opamp) for medium-resolution pipelined Analog-to-Digital Converters (ADCs) in deep-submicron CMOS processes are discussed. Comparisons are made between basic opamp topologies in 130 nm CMOS process, concerning particularly on gain, bandwidth, signal headroom and power consumption with 1.2V supply.