A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density
Q
_inv
and effective mobility μ
_eff
has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e.,
C
_of
and
Cf
(poly-end), respectively. Both categories of parasitic capacitance lead to overestimated
Q
_inv
and underestimated μ
_eff
. The increase in effective channel width
W
_eff
due to Δ
W
from shallow trench isolation (STI) top-corner rounding may compensate μ
_eff
degradation due to STI stress. The tradeoff between μ
_eff
and
W
_eff
determines the impact of width scaling on
I
_DS
and
Gm
. A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μ
_eff
in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.