Viterbi-Based Efficient Test Data Compression

Researchers have proposed numerous test compression techniques that provide comparable fault coverage to that of conventional ATPG and reduce the amount of test data and test time. Among them, the linear-decompression-based schemes have gained popularity for simplicity and high encoding efficiency. However, they lack the knowledge about the effects of compressed test vectors toward other test requirements. We propose a Viterbi based test data compression technique. The on-chip Viterbi decompressors accept n bits from the external tester and apply m bits into internal scan chains (m>;>;n ). Each decompressor needs only one test channel and the encoding efficiency is independent of the number of test channels. During the generation of a compressed test vector, the Viterbi algorithm traces the cost function of each possible compressed vector and decides the most desirable compressed vector. The proposed architecture, thus, presents a platform to combine test compression with other test considerations such as low power consumption, vector repetition.