A low power RF front-end for L1/E1 GPS/Galileo and GLONASS signals in CMOS 65nm technology

This paper presents a low-power RF front-end designed for L1/E1 GPS/Galileo and GLONASS, implemented on 65nm CMOS technology. It draws 28mA on external voltage supply at 1.2V, with power consumption of 33.6mW. The chip could work also at 1.8V using a chip-embedded low dropout regulator (LDO). The device integrates a high performance low noise amplifier (LNA), an automatic gain control (AGC) that doesn't need any external capacitor, and the phase-locked loop (PLL) filter reducing the external components count; only few passives for matching and external TCXO for frequency reference are needed. A programmable synthesizer manages most of the commonly used TCXO frequencies. The device presents only one input for RF signal with two intermediate frequency (IF) chains one for GPS/Galileo signals and the other for GLONASS signals. Both IF filters are fully embedded. The data bit for base band are generated by 3-bits analog-to-digital converters (ADC). The whole die area is 4.65mm
²
.