A low latency high throughput router for On-Chip interconnect networks

A low latency high throughput Dynamic Virtual Output Queues Router for On-Chip interconnect networks is proposed in this paper, which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output queues scheme. Compared to wormhole router and virtual channel router, Simulation results show that network throughput on a 4×4 mesh increases by up to 46.9% and 28.6% respectively, and outperforms doubled buffer virtual channel by 1.9% under same input speedup. Network zero-load-latency also decreases by 25.6% and 41% respectively under random traffic. Synthesis results in TSMC 65nm technology indicate the frequency of router with 0.404mm
²
area can reach 2.5 GHz.