Reduce Leakage Currents in Low Power SRAM Cell Structures

Two static random access memory cells that reduce the static power dissipation due to gate and sub threshold leakage currents are presented. The first cell lowers the leakage currents by using transmission gate and changes in ground level. Second cell lowers the leakage currents using dual-VTH and transmission gate. The whole project is implemented in CMOS 90nm technology.