FPGA-Based Laboratory Assignments for NoC-Based Manycore Systems

Manycore systems have emerged as being one of the dominant architectural trends in next-generation computer systems. These highly parallel systems are expected to be interconnected via packet-based networks-on-chip (NoC). The complexity of such systems poses novel and exciting challenges in academia, as teaching their design requires the students to understand a large number of NoC-based design-space parameters. Moreover, the industry has only recently attempted to design large-scale NoC-based manycore prototypes; the use of NoCs, therefore, has not yet reached a mature stage. Consequently, academia still lacks standardized tools and methodologies to teach NoC-based manycore systems, which, in turn, demand a solid educational background in a wide variety of areas, thus raising several teaching challenges. This paper presents an FPGA-based teaching framework composed of a sequence of laboratory assignments. The framework provides instructors with a practical teaching approach and helps them teach students how to emulate NoC-based manycore systems and how to evaluate and explore their design parameters. The proposed framework can be integrated into existing senior undergraduate courses or can be taught as an independent course. The course has been taught three times at the University of Cyprus, and initial course evaluation results, instructor observations, and suggested grading policies are also provided.