Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators

This paper introduces Interconnect Physical Analyser (IPAA) - a tool for the analysis and optimisation of SoC/NoC toplevel interconnect. IPAA extracts information from the IC router and power analysis tool after implementation. Combining information from both sources, the tool performs a wirelength-driven power analysis of toplevel interconnect in the design. A range of statistics for toplevel interconnect is reported and a set of plots is produced. Multiple designs can be analysed simultaneously, enabling comparison and optimisation. The tool is applied to the design of scalable, efficient bus-replacement Network-on-Chip interconnect for Public Key Cryptographic accelerators. IPAA analyses the physical effects of scaling the cryptographic accelerator's floorplan, the number of cores and the cryptographic wordlength. The tool's plots and reports highlight the efficiency and scalability of the bus replacement Network-on-Chip and help guide the optimisation of the design.