Analysis of dual Gate Mosfets using high k dielectrics

Double Gate (DG) MOSFETs are used for CMOS applications beyond the 70 nm node of the SIA roadmap because of their excellent scalability and better immunity to short channel effects. To reduce the short channel effects, the device performance is analyzed by replacing the SiO2 with various high-k materials and the gate oxide thickness is scaled so that they have the same equivalent Oxide Thickness (EOT). The device shows improved Ion /Ioff ratio. The use of high k dielectrics in MOSFETs reduces the EOT and double gate device gives better controllability. High-k dielectric materials have equivalent oxide thickness (EOT) of 1.0nm with negligible gate oxide leakage, desirable transistor threshold voltages for n and p-channel MOSFETs, and transistor channel mobility close to those of SiO2. Possible high-K materials are SiO2 (k∼3.9)„Al2O3 (K∼10), HfO2/ZrO2 (K∼25) which provide higher physical thickness and reduce the direct tunneling leakage current. So in this paper we study the effect of introduction of wide range of proposed high-k gate dielectrics on the device.