A novel parallel architecture for low voltage-low power DLL-based frequency multiplier

New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating big multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the multiplier is adopted to create the 13 times of the reference frequency. The circuit level design is presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13 um CMOS Technology.