FPGA implementation of a channel noise canceller for image transmission

An FPGA-based channel noise canceller using a fixed-point standard-LMS algorithm for image transmission is proposed. The proposed core is designed in VHDL93 language as basis of FIR adaptive filter. The proposed model uses 12-bits word-length for digital input data while internal computations are based on 17-bits word-length because of considering guard bits to prevent overflow. The designed core is FPGA-brand-independent, thus can be implemented on any brand to create a system-on-programmable-chip (SoPC). In this paper, XILINX SPARTAN3E and VIRTEX4 FPGA series are used as implementation platform. A discussion is made on DSP, Hardware/Software co-design and pure-hardware implementations. Although using a pure-hardware implementation results in better performance, it is more complex than other structures. Results obtained show improvements in area-resource utilization, convergence speed and performance in the designed pure-hardware channel noise canceller core.