A 6-mW 10-bit 300 ksamples/s pipeline A/D-converter

This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from a 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +- 1.5 LSB and DNL +/- 0.5 LSB. The active chip area is 1.3 mm/sup 2/, excluding pads.