A 3.3 V-70 MHz low power 8 bit CMOS digital to analog converter with two-stage current cell matrix structure

This paper describes a 3.3 V-70 MHz low power 8 bit CMOS digital to analog converter (DAC) designed with a 4 MSB current matrix stage and a 4 LSB current matrix stage. The two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the number of current sources. Fast settling time and low power consumption of the DAC are achieved by utilizing the proposed architecture. The simulation results of the designed 8 bit DAC show a conversion rate of 70 MHz and a power dissipation of 24.5 mW with a single power supply of 3.3 V for a CMOS 1.5 /spl mu/m n-well technology.