A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS

An architectural solution for designing a low-reference-spur PLL is presented. A spur frequency-booster block is inserted between the phase-frequency-detector and the charge pump to boost the charge pump's input frequency. Hence, the reference-spurs theoretically vanish. The proposed technique adds additional degrees of freedom in the design of PLLs to reduce the spur level without sacrificing neither the loop bandwidth nor the voltage-controlled oscillator's gain. A prototype is fabricated using UMC 90 nm digital CMOS technology and achieves -74 dBc reference-spur suppression along with (K
_VCO
/f
_ref
) ratio of 17 at a (f
_BW
/f
_ref
) ratio of 1/20.