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A 130nm CMOS 100Hz–6GHz reconfigurable Vector Signal Analyzer and Software-Defined Receiver | IEEE Conference Publication | IEEE Xplore

A 130nm CMOS 100Hz–6GHz reconfigurable Vector Signal Analyzer and Software-Defined Receiver


Abstract:

A monolithic 100Hz-6GHz reconfigurable Vector Signal Analyzer (VSA) and Software Defined Receiver (SDR), following a two-step up-down conversion heterodyne scheme with ro...Show More

Abstract:

A monolithic 100Hz-6GHz reconfigurable Vector Signal Analyzer (VSA) and Software Defined Receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wide-band interference scenarios, is presented. The 130nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or harmonics. A monolithic VSA/SDR enables various commercial and military wireless solutions.
Date of Conference: 05-07 June 2011
Date Added to IEEE Xplore: 04 July 2011
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Conference Location: Baltimore, MD, USA

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