All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator

A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm
²
. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.