Impact of through-silicon-via scaling on the wirelength distribution of current and future 3D ICs

In this paper, we investigate the impact of TSV scaling on the wirelength distribution of the 3D ICs. This investigation includes wirelength distribution prediction of 3D ICs for current/future process/TSV technologies, studies on the impact of the design granularity at each process node, the impact of the die count, and the impact of TSV area constraint, and cross-comparison among various 2D and 3D technologies.