A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters

A novel ripple mitigation technique is proposed for switched-capacitor voltage regulators (SCVR), which eliminates the output voltage ripple without using multi-phase interleaving. An inner control loop matches the SCVR's switch current to the load current on a cycle by cycle basis. A 2-phase 3:2 SCVR is designed in 45-nm CMOS process with the proposed control. For a 1.8 V to 1.05 V /40 mA converter, the proposed mitigation loop reduces the peak-to-peak output ripple from 330 mV
_p-p
to 17 mV
_p-p
, using total output capacitance of 4 nF/A. In addition, the proposed technique yields excellent regulation transient response.