A digital implementation of self-organizing maps

A digital implementation of self-organizing maps is presented. The chip designed includes 32 neurons with 1024 16-bit weights and 8-bit inputs. Each neutron performs bit-serial processing to minimize the occupied silicon area. Several chips can be interconnected to expand the number of neurons in the network. The number of inputs per neuron depends on the internal weight memory size. The dimensionality of the network the neighbourhood topology and the rate at which the neighbouring cells learn, are programmable. The design was realised using the cells of the ES2 ecpd10 Library and simulated with Verilog. The estimated operation speed is 0.7 MCUPS/mm/sup 2/ during the learning phase, and 1.95 MCPS/mm/sup 2/ during the recall phase.