Enhancement of the weight cell utilization for CMAC neural networks: architecture design and hardware implementation

CMAC neural network model has the advantages of fast learning and insensitivity to the order of presentation of training data. However, it may suffer from a huge storage requirement for realizing the weight cell memory. In this paper, we propose a memory banking structure and a direct weight cell address mapping scheme, which can sharply reduce the required address space of weight cell memory. This mapping scheme also exhibits a fast computation speed in generating weight cell addresses. Besides, a pipelined architecture is developed to realize the CMAC chip. To efficiently manage design complexity and increase design productivity and maintainability, a high-level synthesis technique is adopted to perform the task of logic design of the CMAC chip.