Matching properties of CMOS SOI transistors

Analog implementations of neural networks have shown promising results; the main drawback of such techniques is the limited accuracy available in standard analog technologies. A test circuit composed of 256 N-channel and P-channel transistors has been designed and tested in an SOI (Silicon-On-Insulator) CMOS 3 /spl mu/m technology. This paper describes the matching properties of these current sources. We present results about mismatching depending on proximity and operating conditions. We also propose a method to compute the matching behavior of multiple current mirrors.