Integrating Memory And Network Accesses : A Flexible Processor-network Interface For Efficient Application Execution

It has been shown that the large communication overhead in current multicomputer systems can be reduced greatly by using proper communication mechanisms [l] and processor-network interfaces [4]. A good processor-network interface design is highly dependent on application characteristics, programming model, memory interface, and routing characteristics of the network. Unfortunately, these issues are not exploited fully in the previous work. In this paper, we address these issues from the perspective of application performance and propose a processor-network interface architecture that to optimize the system performance. Through such a design, not only the processor and network are tightly coupled, also are memory operation and message passing. As a result, high-level operations such as gather and scatter can be supported easily instead of using low level operations proposed previously