A simple and fast scheduler for input queued ATM switches

Many 'output scheduling' algorithms have been proposed for improving the performance of input-queued asynchronous transfer mode (ATM) switches, whereby cells from different random-access input queues destined for the same output can be scheduled for non-conflicting transmissions. An optimal output scheduling algorithm, with full coordination of transmission to all outputs, can approach the performance of output queueing. Because of the complexity of such an optimal scheduler, the output schedulers proposed in the literature are without such coordination. We propose a simple way to incorporate such a full coordination in output scheduling with very simple hardware. The throughput of the input queuing switch thus approaches that of the output queueing switch, without speed-up, input/ouput grouping or complicated hardware. To make the output scheduling algorithm fast enough, we incorporate parallelism and pipelining. We perform a detailed simulation study of the performance of the input queueing switch with the proposed scheduling algorithm.