Test structure for mismatch characterization of MOS transistors in subthreshold regime

This paper proposes a simple test circuit for characterization of MOS transistor mismatch in a standard 2 /spl mu/m CMOS technology. Measurements have been performed both in the saturation and subthreshold regimes in order to obtain an accurate characterization in a wide range of operations. The parameter mismatch estimation algorithm is based on Multiple Linear Regression and is able to furnish information on the estimation accuracy.