Test chip and data considerations for MOS parameter extraction

This paper presents an investigation of principles for test chip design and data point selection for MOS parameter extraction methods using a low number of data points. Variations in extracted parameter values for different combinations and numbers of data points are studied experimentally. The influences on the standard deviations of V/sub T/, /spl beta/, /spl theta/, R/sub S/, /spl Delta/W and /spl Delta/L of different data point selections and device combinations are studied using synthetic data with multiplicative noise.