Issues on short circuits in large on-chip power MOS-transistors using a modified checkerboard test structure

To control random quality deviation of large on-chip power MOS-transistors, we have developed a modified checkerboard test structure. Using this structure, the complete chip area is divided into distinguishable subchips, each containing one large area power MOS-transistor. The fast digital measurements and the precise localization of transistor short circuits guarantee a fast process classification and enable additional electrical and optical defect parameter extraction.