Integrated test circuit to measure polarization characteristics of ferroelectric capacitors for development of mega-bit scale FeRAM

This paper proposes an integrated test circuit to measure the polarization characteristics of ferroelectric capacitors on a silicon substrate for the development of mega-bit scale nonvolatile ferroelectric random access memories (FeRAMs). The test circuit consists of a Sawyer-Tower circuit and a pulse generator. Three example applications of the test circuit were used to evaluate the nonvolatile polarization (Pnv) of single SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) capacitors. First, the Pnv of SET capacitors with areas ranging from 3.82 /spl mu/m/sup 2/ to 64 /spl mu/m/sup 2/ were measured to investigate the area dependence of Pnv deviations. Second, Pnv were measured as a function of writing pulse width to determine polarization reversal response. Finally, acceleration fatigue tests were carried out on SBT capacitors with stress pulses set at 75 MHz.