Space/time adaptive processing architecture implementations using a high performance scalable computer

Pre and post-Doppler STAP architectures are considered for a target implementation on an Analog Devices super-Harvard architecture (SHARC) based high performance scalable computer utilizing a Myrinet/sup TM/ communications network. Mapping and partitioning tasks perform an initial feasibility and sizing analysis for an implementation which performs both architectures on the same hardware. Further modelling and simulation studies utilize a discrete event simulator to perform detailed analyses of three different block and sample recursive algorithm mappings onto the target hardware in order to obtain insight into processor and communication utilization and data latency.