A 622 Mb/s 32/spl times/32 scalable shared buffer ATM switch with searchable address queue

The advanced 0.5-/spl mu/m CMOS technology makes it possible to integrate a huge amount of memories and enables us to apply sophisticated architecture. The implementation of the ATM switch chipset, using new architectures named funnel-structured expandable architecture and the searchable address queueing scheme, is described. A 622 Mb/s 32/spl times/8 element switch consists of one buffer LSI and one control LSI. A 622 Mb/s 32/spl times/32 switch which comprises four element switches can be installed in one board. The switch has delay-priority control, cell-loss priority control, multicasting function and hierarchical queueing function to accommodate 156 Mb/s, 622 Mb/s and 2.4 Gb/s interfaces.